1. Field of the Invention
The invention relates generally to the vertical semiconductor power devices. More particularly, this invention relates to configurations and methods with improved manufacturability for manufacturing vertical semiconductor power devices with a super-junction structure for high voltage applications.
2. Description of the Prior Art
Conventional manufacturing technologies and device configuration to further increase the breakdown voltage with reduced series resistance with a super-junction configuration are still confronted with difficulties and limitations of manufacturability. The practical applications and usefulness of the high voltage semiconductor power devices are limited due to the facts that the conventional high power devices manufactured with super-junction structural features now encounter difficulties to satisfy the more stringent processing windows. Specifically, when the target RdsA is reduced from 20 mohm/cm2 to 10 mohm/cm2, the allowable charge balance variation is reduced from 30% to 10%. However, the conventional techniques cannot achieve such requirements due to the variation of the N charge for doping the epitaxial layer. When the conventional double implant processes are applied to form the super-junction, a variation of N charge for doping the epitaxial layer can be controlled within 1% to 2%. However, due to the variation of the critical dimension (CD) in controlling the alignment of the dopant implantations, especially for devices with small pitches, the charge variation may increase to 10 to 20% when multiple implant masks are applied using conventional manufacturing process. The performance of the super-junction is adversary affected due to the uncontrollable variations of the N charge in the epitaxial layer cannot be further reduced.
FIG. 1A shows a semiconductor power device disclosed in U.S. Pat. No. 5,216,275, to Chen. The semiconductor power device is supported on a superjunction structure formed as composite buffer (CB) layer comprises N and P doped regions. However, the variations of charges between the P-doped regions and the N-doped regions in the super-junction structure are significantly beyond the device requirements as now used in the device for more modern applications. For example, as that included in one of the claims, the semiconductor power device that includes the first and second semiconductor regions are doped with dopants and the total charge of the effective dopant concentration in the first semiconductor region does not exceed the total charge of the effective dopant concentration of the second semiconductor region by 50%. The disclosures of Chen therefore cannot satisfy the more stringent device requirements as now imposed on such devices.
FIG. 1B shows another super junction device disclosed by Deboy in U.S. Pat. No. 6,960,798. As shown in FIG. 1B, the cross sectional view of a cell design of the super-junction structure has a drain D, a source S, and a gate G, the n+ conductive semiconductor substrate 1, an n-conductive semiconductor region 13, the n-conductive layer 3, and n-conductive regions 4 as well as p-conductive regions 5 under the source electrode S. The degrees of compensation, for example, between +30% and −20% are reported, whereby a degree of compensation “0” indicates true compensation between n-doping and p-doping. Here, the doping thus varies within the “p-column” by a factor 3 whereas the doping in the “n-columns” is constant. Such dopant variations, even with compensations as disclosed would still not be satisfactory to meet the requirements of current applications with more stringent design windows.
FIG. 1C shows a cross sectional view of a multiple epitaxial superjunction structure formed by a conventional manufacturing process. The method includes a first step of growing a first N-epitaxial layer 320-1 on an N-substrate 310; a second step of applying a first implant mask 300 to open a plurality of implant windows 315 to implant a plurality of P-dopant regions 330-1 in the first N-epitaxial layer 320-1; the first step and the second step are repeated with the second N-epitaxial layer 320-2 formed on top of the first N-epitaxial layer 320-1 and so on. The P-dopant regions are diffused to merge the P-dopant regions 330 as doped columns in the N-epitaxial layers 320. However, in this method, due to the variation of the critical dimension (CD) in controlling the alignment of the dopant implantations, the total charge variation may increase.
Since the super-junction devices can significant reduce the on resistance of the semiconductor power devices, there is a great demand for such power devices for applications on devices required for power savings, particularly in portable electronic devices.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new device configurations and manufacturing method in forming the power devices supported on a super-junction structure such that the above discussed problems and limitations can be resolved.